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RM0008
Connectivity line devices: reset and clock control (RCC)
Bit 18 HSIRDYC : HSI ready interrupt clear
This bit is set by software to clear the HSIRDYF flag.
0: No effect
1: Clear HSIRDYF flag
Bit 17 LSERDYC : LSE ready interrupt clear
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: Clear LSERDYF flag
Bit 16 LSIRDYC : LSI ready interrupt clear
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: Clear LSIRDYF flag
Bit 15 Reserved, always read as 0.
Bit 14 PLL3RDYIE : PLL3 Ready Interrupt Enable
Set and cleared by software to enable/disable interrupt caused by PLL3 lock.
0: PLL3 lock interrupt disabled
1: PLL3 lock interrupt enabled
Bit 13 PLL2RDYIE : PLL2 Ready Interrupt Enable
Set and cleared by software to enable/disable interrupt caused by PLL2 lock.
0: PLL2 lock interrupt disabled
1: PLL2 lock interrupt enabled
Bit 12 PLLRDYIE : PLL ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
Bit 11 HSERDYIE : HSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the external 3-25 MHz
oscillator stabilization.
0: HSE ready interrupt disabled
1: HSE ready interrupt enabled
Bit 10 HSIRDYIE : HSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the internal 8 MHz RC
oscillator stabilization.
0: HSI ready interrupt disabled
1: HSI ready interrupt enabled
Bit 9 LSERDYIE : LSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the external 32 kHz
oscillator stabilization.
0: LSE ready interrupt disabled
1: LSE ready interrupt enabled
Bit 8 LSIRDYIE : LSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by internal RC 40 kHz
oscillator stabilization.
0: LSI ready interrupt disabled
1: LSI ready interrupt enabled
Doc ID 13902 Rev 9
119/995
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